Jitter suppression and PLL design

In high-end audio DAC design, `jitter' is known to have a negative influence on the perceived sound quality. Clearly, when restoring an analog signal from a sequence of samples, the accuracy of the timepoints at which the samples are converted is as important as the accuracy in the amplitude domain. In the next three sections we will explain 1) what `jitter' is and where it originates from, 2) how to tackle the problem by an extra PLL (Phase Locked Loop) and what its filter characteristics should be, and 3) how this is implemented as actual circuit.

What is jitter; where does it come from

It is reported that timing errors in the order of 100 ps are perceptible [Watk94]. Some others claim jitter to be audible down to the few picosecond range, also depending upon the spectral content of the jitter.

Now CD players (transports) output their digital data from a buffer, clocked by a crystal oscillator. This data buffer is kept (partially) filled by a feedback-loop controlling the CD spindle speed. Since well-designed crystal oscillators are able to generate highly stable clocks, the digital data could be sent out with a low level of jitter. Any built-in DA converter would use the same crystal-controlled clock, and hence inside the transport good jitter suppression should be feasible.

However when going to external DACs, we have an additional problem. The connection from the CD player to the external DAC is done with a single coaxial wire, carrying a coded serial bitstream according to the S/PDIF standard. In the DAC, this signal is processed by some receiver chip, which has as main task to regenerate a clock signal from the data stream, and use this same clock to latch the incoming bitstream. This is the first point where the `jitter' is created: in the clock generation circuitry of the S/PDIF receiver chip. There is a combination of several factors, which in combination are responsible for the jitter generation at this stage:

  1. The S/PDIF input bitstream arrives at a reasonable high rate of about 2.8 Mbit/sec. Due to the limited bandwith (parasitic capacitance) of the interconnect (plugs and cables), the signal arrives with a degraded slope. This gives uncertainty in the exact determination of the clock edge timepoint. This is also a reason why different cables can sound differently.
  2. The S/PDIF signal is coded to become DC-free. As result it can be (and is) AC-coupled through small isolation transformers and input capacitors. However the lower frequency components can cause variations in the moments where the (limited slope) input signal voltage crosses the reference potential, and thus time shifts in the (amplified) edge. These time shifts would depend upon the actual (sequence of) bit values.
  3. The clock is regenerated in the receiver chip with a PLL circuit. However the on-chip oscillator timing is capacitor-based and not crystal-based. As result it generates significant jitter of its own.
  4. The dynamic characteristics of the receiver PLL are to ensure an error-free clocking of the actual bit values. The dynamic properties of the PLL filter are normally configured with an external resistor and capacitor. These are to be given prescribed values of cheap and small components, causing the PLL to regulate (allow changes in its clock frequency) in the audio range. This seems a bad choice.
  5. The applied external RC PLL filter seems just configured for its dynamic properties, according to standard textbook PLL design. When jitter is of concern however, better low-pass filters can sometimes be used.

The above points 3 to 5 in principal depend upon the actual receiver chip selected. However both the Yamaha YM3623B and the Crystal CS8412 considered by us, are comparable in this respect. Their simple and cheap clock recovery can be motivated by the reasoning that the purpose of the PLL is to clock-in the correct values of the bitstream. To accomplish this, a jitter of half a bit width (170nsec) would be still acceptable. For high-end audio applications they might rightfully expect different circuitry for another more stable clock to drive the DAC chips.

When the recovered signal is processed further by a digital filter, more jitter is introduced. The delay time of logic gates (in the normally used CMOS technologies) strongly depends upon their supply voltage. This means that momentarily dips in the supply voltage as caused by internal switching activity cause timing variations. Furthermore noise in the external power-supply regulators is a cause of jitter. As result, jitter generated in the digital filter circuitry can easily be of same order of magnitude as the jitter which originates in the input receiver.

Jitter removal with an extra PLL

In our DAC design, an extra PLL circuit is used to generate a stable low-jitter clock for the output circuitry. In this section we will give some background how a PLL works, and what design constraints will lead to a low-jitter clock. A general diagram of a Phase Locked Loop circuit is shown below:

Standard PLL circuit

The `frequency divider' is used for applications (as our DAC) where the output frequency must be higher than the input frequency. In normal operation the PLL should be `in lock', which means that the (divided) output frequency is identical to the input frequency, and that the feedback loop controls phase variations between these two signals. The way phase variations in the input signal influence phase variations on the output is most easily derived in the frequency domain, which is also suitable to analyse the stability of the feedback loop.

For the frequency domain analysis of the PLL, it can be handled as any feedback system:

Feedback system

The overall transfer characteristics of such a feedback system is: H(s) = A(s) / (1 + A(s).B(s)) . The `open loop gain' is defined as OG(s) = A(s).B(s) .

For the PLL, the phase detector functions as the initial adder of the feedback system. It is characterized by a gain Kp in units of [V/rad]: It has a static, linear transfer within a limited phase margin. For the flipflop based detector which we use, the phase margin is 2 full periods, or 4π radials.

For the filter we will use a later to be defined characteristic LPF(s) .

The voltage controlled oscillator behaves in terms of phase as an integrator, and has a transfer characteristic of VCO(s) = Ko/s [rad/V] , where Ko is called the VCO gain.

The frequency divider is simply characterised by its division ratio Ndiv .

As result we have: A(s) = Kp Ko LPF(s) / s , and B (s) = 1/Ndiv .

For the dynamic characteristics of the closed-loop system, it is attractive to study the open-loop gain OG(s) . The `cut-off' frequency fc above which this gain || OG(s) || drops below 1, determines the closed-loop bandwidth. For a stable system, the phase Arg(OG(2πfc)) should not be significantly larger than π /2 , or, in other words, || OG(s) || should decrease as a first order system, at frequencies around fc . Since VCO(s) already decreases with s , it is required that LPF(s) remains constant around fc . This is shown in the following figure.

Frequency dependent components of the PLL open-loop gain

The open loop gain is:

Having just a first-order LPF, drawn with only two segments (decreasing until fL , then remaining constant for all higher frequencies, omitting the fh corner), is a textbook standard PLL filter. This results in a 2nd order feedback system, which can still be analyticalized by hand. The series RC section often connected to a receiver chip, clearly demonstrates the use of such a filter. Although this might be fine for certain dynamic 'lock-in' properties, this is not good enough for low-jitter requirements, which is motivated below.

If we look at the overall phase response of the PLL H(s) , then H(s) is about 1/B(s) is NDiv for frequencies below fc . This means that changes in phase (in the time-point of the clocksignal edges) appear unmodified at the PLL output, for changes with frequency components slower than fc . (The ratio NDiv only relates absolute changes in time (phase) to the frequency, and our analyses is clearer when normalised away.)

PLL overall phase response as function of frequency

On the other hand, for frequencies above fc, H(s) is about A(s), and follows the same characteristics as OG(s) drawn above. This shows a first-order low-pass characteristic, with cut-off frequency fc, even if LPF(s) would remain horizontal (constant) above fc. This is according to standard PLL filters. However if phase jitter is of concern, it is FAR better to use an LPF which has a low-pass characteristic of its own, for instance with a cut-off frequency fh as shown in the above drawings. In that case, the overall PLL H(s) will drop as second-order filter for frequencies above fh. As shown later, our design will have two more low-pass filtering components, coming in at a higher frequency fH, creating an overall 4rd order low-pass PLL characteristic.

It is easily seen that inserting these higher-order low-pass components at fh and fH do not influence the stability of the PLL feedback loop, if they are significantly larger than fc: At fh the open-loop gain is already dropped significantly below 1 and the feedback has become ineffective.

At this point you should be convinced that a PLL can filter away jitter from the input signal for frequency components above fc, and that using a higher-order low-pass LPF is usefull to achieve an overall higher-order jitter suppression.

However there is another important motivation for wanting a truly low-pass filter for LPF, which is not often mentioned. In the formulas above, the phase detector is assumed to return an output voltage which is linear with the phase difference of both signals to compare. In practice (for digital signals) the phase comparator is normally made with digital circuits. The output of such a comparator is a pulsed (variable duty-cycle) signal, of which the average value has the desired linear phase relation. For low-jitter applications it is important that the PLL filter effectively smooths this phase comparator signal to a stable (low ripple) value, since any ripple (AC component) on the VCO input directly (by definition) generates new jitter on the oscillator (PLL) output! A badly designed PLL could introduce more jitter of its own, than it suppresses from its input. This is a clear reason to need the fh corner frequency in the LFP filter curve.

In our design the PLL operates on a 16x divided master clock frequency, or 11.289MHz / 16 = 705 kHz. For optimal jitter suppression the fc frequency should be many orders of magnitude below that. Since the human ear is very sensitive for frequency modulation, and the PLL output will be used to clock the DA converter chips, it seems natural to choose fc really below the audible frequencies. We chose fc near 1 Hz. As result audio frequency components in the jitter are strongly reduced.

A final motivation is probably still needed for wanting the PLL filter to have increasing gain for lower frequencies, below fc: Why should the filter behave for very low frequencies as an ideal integrator, with a gain towards infinity for frequencies towards zero?

One of the two answers to this question is also in the particular choice of the phase comparator. The chosen comparator is built with two flipflops, and generates positive or negative pulses, in width proportional to the phase error. When both inputs are equal in phase, the pulses vanish to zero width. As result the AC frequency components in the phase comparator output also vanish in amplitude at zero phase difference. This is an important and nice property for low-jitter frequency generation: this leads to a stable input control voltage for the VCO. Thus we prefer a zero phase difference when the PLL is in lock: an integrating filter will then have some (nonzero) constant output voltage, appropriate to regulate the VCO frequency identical to the input frequency. The required VCO input voltage to accomplish this, would depend upon component (crystal and capacitor) value variations. The filter should thus be able to provide ANY constant output voltage level with real zero input voltage (zero pulse width). Clearly this corresponds to an ideal integrator. For stability reasons, as explained above, the integrator frequency fL must be significantly lower than fc.

A second reason for wanting an integrator behavior of the LPF is in acquiring lock. When the circuit is switched on, there will be initially no lock, as the received frequency will differ from the VCXO frequency. Many phase comparator types will then produce an output signal proportional to the phase difference, consisting of an AC signal with frequency components down to the input frequency difference, and no DC component. As the input frequency difference (lets say 1kHz) is in our case many orders of magnitude larger than the LPF corner frequency (a few Hz), the LPF filters away all phase comparator output, and no suitable control remains for the VCXO. As result, the circuit would not move to a lock state, with a VCXO frequency equal to the input frequency. To solve this problem, a phase comparator type is needed which also provides an avarage output value corresponding to the frequency difference. This is accomplished by a (well known) flip-flop type phase comparator. However the DC output value due to a frequency difference is very small, and only true integration of this value leads to enough control voltage to drive the VCXO in frequency lock.

Implementing the PLL

In this section the final circuit realisation of the PLL and its use in the complete DAC is explained and motivated. This is done in the four following paragraphs describing the overall view, the voltage-controlled oscillator and divider, the phase comparator, and the filter.

The overall view

When an extra PLL is used to obtain a cleaner clock, it is not immediatly evident how and where this clocksignal should be used, in cooperation with the 'dirty' clock from the receiver: At some point the DAC system should be partitioned by a buffer. The input part of the DAC, including filling the buffer, should then operate on the dirty clock, and the output part of the DAC, starting at reading the buffer, should operate at the clean clock. The buffer size can be chosen between 1 bit of the serial audio stream, 1 sample-word per channel, or a large queue of many sample words.

For our design we chose to use the sample word buffer: Having the PLL in phase-lock on the word clock (44.1 kHz), does not require longer buffer queues. Operating the PLL on the input bit-clock (32 bits x 2 samples x44.1 kHz = 2.8224 MHz) would have been another usefull option but would leave a small phase (timing) margin for the very slow changing oscillator frequency. Furthermore we wanted to make a truly high-quality design with relatively few components. It appeared that the Nippon `SM5842AP' could not only provide high audio quality filtering (such as 32-bit accuracy mathematics), but also provided the option of operating on a dual clock with an internal word buffer. It has a relatively small input circuit section operating on the 'dirty' input clock, a word buffer, and then the data processing and output on a second 'clean' clock. Its datasheet specifies a maximum allowable 3/8 period difference between both clocks. This allows easy cooperation with an external PLL locking on the word clock. The resulting system overview is presented in Figure 5.

Note that regarding the bit rates, serial transmission always assumes 32 bits, irrespective of the actual number of used and valid data bits (16 for CD playing, optionally 18 for DCC playing, 20 from the digital filter to the dac chips). The required clock for the output bit rate is thus 32 bits x 8 way oversampling x 44.1 kHz sample rate is 11.2896 MHz.

Besides a clock-signal, the PLL also provides a signal indicating whether the PLL is really in lock. An out-of-lock condition leads to a visible (LED) indication, and muting of the filter audio output. Besides for out-of-spec crystals or large temperature differences, this will in particular happen when SP/DIF input signals are applied of different sample frequency. The 44.1 kHz sample frequency is standard for normal CD and DCC players. Besides that, DCC players and the MPEG-2 standard also support 32 and 48 kHz sample rates. This 48 kHz is used in some professional equipment (in particular DAT recorders), and will be used for the intended European Digital Audio Broadcasting. Newer standards for high-end audio specify sample rates of 96 and 192 kHz.

To allow operation on 48 kHz sample rates and multiples of that, the system can in principle be extended with a second PLL with a different crystal frequency, to lock on a 48 kHz input frequency, and correspondingly switch the digital filter to the desired clock. However this would imply a significant redesign.

The voltage-controlled oscillator and divider

The VCO is built as a crystal oscillator, since crystal oscillators are well known for their high frequency stability (is low jitter). They obtain this stability from a very high Q resonance, electrically modelled as a series connection of a high-Q inductor and capacitor (with a larger capacitor in parallel with this). The resonance frequency of this circuit can be tuned over a (very small) interval by a variable external capacitor. The nominal center frequency of the crystal is typically obtained with a 30 pF external parallel capacitor, with higher values giving slightly lower frequencies and vice versa. This is shown in Figure 6:

Our very first VCO was built with a digital oscillator & divider IC, indicated in figure 7 below. This circuit is not used anymore in our DAC, and shown here as example for principle of operation only. The 220p capacitors isolate the DC operating point of the nand-gate from the DC control voltage applied to the capacitance diodes. Furthermore they implement an upper limit on the combined (effective) capacitance in parallel to the crystal, thus taking care of a lower bound on the gain (Q factor), making sure the oscillation will never die. As side effect the AC amplitude of the oscillation voltage across the capacitor diodes reduces when they are driven to higher capacitances, which nicely fits to the correspondingly reduced DC reverse voltage. The 10n capacitor grounds the oscillator signal, and forms a low-pass filter with the 220k resistor on the control-input, filtering out high frequency components in both directions (from the phase comparator to the oscillator and back). The BB212 provides typically a 10pF to 500pF capacitance range for each diode, when applied a 12V to 0V reverse voltage. Using a control voltage up to 12 V is unfortunately required to drop to low capacitances: allowing only a 0-5 volt range, the capacitances remain too high, giving unsatisfactory frequency control. The 74HC(T)4060 part is specified to work up to about 90 MHz, which provides enough safety margin for good crystal operation. The measured Vcontrol to frequency curve is shown in Figure 20.

Unfortunately the performance of a 4060 (or any cmos logic ) type oscillator is unsatisfacory, as we learned later. To obtain a really stable low jitter clock better crystal oscillator circuits are needed, typically built with discrete components. To obtain a low jitter (or low phase noise) crystal oscillator, the following design goals should be taken into account:

  1. The high Q-factor of the crystal must be maintained in the circuit, which means that the series-resistance of the surrounding (driving) circuit must be low (lets say below 50 ohms).
  2. It should operate with low-distortion sine-wave signals, not block-style signals from digital gates. The additional high-frequency components disturb a clean oscillation.
  3. The active components providing oscillation gain must be low-noise devices.
  4. The AC current through the crystal must be controlled (limited) to a small value, typically not exceeding 1 mA. This requires some attention when a low drive impedance is used.

All integrated cmos-logic oscillators certainly violate points 1, 2 and 3, and maybe also 4.

Although we have built such oscillators, we finally found good ready-to-use VCXO modules, which saved considerable PCB space over discretely built oscillators.

The now used VCXO modules operate on a single 5 volt supply voltage, and have a control input in the 0 to 5 volt range. Although a frequency range of +/- 100 ppm (is +/- 0.01%) was specified, we measured a reachable frequency range of about +/- 150 ppm. The resulting VCO gain Ko is about 10-4 x 11.28[MHz] x 2π [rad]/ 2 [V] = 3.5 x 103 [rad/s.V].

The phase comparator

In the PLL feedback system, the phase comparator has the important task of delivering an output signal proportional to the phase difference of both input signals. In our context we have the (often encountered) situation where both signals are digital: generated by logic circuits. A popular PLL digital phase detector is the 'phase detector 2' in the (74HC(T))4046, consisting of 2 flip-flops and a feed-back gate for reset. In frequency lock, such a circuit provides a pulsed output voltage, where the duty-cycle corresponds with the phase difference of the input signals over a full period. This corresponds to an average output voltage which is linear with the phase difference. The phase comparator gain Kp = 5 [Volt] / 4π [rad] = 0.4 [V/rad]. In our case, we made a double differential version of this phase comparator for reduced power supply influence, leading to a gain Kp = 0.8 [V/rad].

Furthermore, when not (yet) in frequency lock, the average output voltage is proportional to the frequency deviation: Vout,average = 5 [Volt] x (1 + (fa - fb)/fa), with fa and fb the different high respectively low input frequencies (this formula is hardly ever shown!).

A phase comparator in this style is provided by several IC's such as the abundantly used (74HC(T))4046, and the newer 7046 and 9046. The 7046 has a lock detect circuit as advantage over the 4046, allowing visual feedback on proper operation. The 9046 does not have this lock detector, but provides a more accurate phase detector with a current-mode output which should result in better jitter figures.

However we built the phase detector with a bunch of more basic logic IC's. Our differential design should provide good power supply rejection. Furthermore our lock detection circuit distinguishes between a too high versus a too low VCXO frequency, on a bi-color LED. This has often helped us in solving problems during the design and test phase.

The PLL filter

The PLL loop filter has three main design parameters: First the (almost flat) gain A around the PLL cut-off frequency fc. Furthermore there are the low and high corner frequencies fL and fh, delimiting the flat gain region. (See following figure)

The PLL cut-off frequency fc is defined as the frequency for which OG(s) becomes 1:
A Kp K0 / Ndiv 2π fc = 1. With K0 from the above measured VCXO curve as K0 = 3.5 103[rad/Vs], our PLL frequency divider of Ndiv = 16, and the phase detector gain Kp = 0.8 [V/rad], this leads to: A = fc / 28.

Note however that for locking with external sources with off-nominal frequencies, the value K0 (the slope of the VCXO curve), gets a lower value, and as result fc will go down. To keep fh and fL significantly away from fc we plan: fL = 0.2 fc, and fh = 3 fc.

Filter circuit 1

A simplified version of the filter structure is depicted in figure 9.

Simplified filter circuit

The chosen filter structure is symmetrical: a common-mode (shared) input value on both Vin+ and Vin- will not contribute to the output voltage. This helps for improving power supply rejection. If the two flip-flops of the phase detector are both not set, or both set, Vin+ and Vin- will have a value of 1/2 Vcc. If only the U13 flip-flop is set, Vin+ changes to Vcc and Vin- changes to 0, and if only the U14 flipflop is set, the other way around.

Due to the large input resistors and low noise requirements, special care is required towards low input leakage currents:

Overall PLL parameters

The closed-loop corner frequency of the PLL fc is now:

fc = 28 x A = 28 / 20 = 1.4 Hz.

fh, the frequency at which the close-loop gain will start dropping at a 2nd order slope, is 5Hz.

Additional filter sections

In reality, our low-pass filter has two more filter sections.

The two input resistors denoted earlier 'R1' are in the actual circuit an aggregate of several components:

The 6 input resistors and 3 capacitors provide an initial passive low-pass filter. A low-pass corner frequency of 10Hz is achieved for differential input signals, and a corner frequency of 100Hz is obtained for common-mode input signals. As the actual input signal is a 705kHz digital signal with lots of higher harmonics, these AC components are significantly damped before reaching the opamp.

A final RC section between the opamp and the VCXO control input again implements a 10Hz low-pass corner frequency. Its main task is to filter out the noise which was generated by the opamp.

Lock detector

Besides two flip-flops and a nand-gate for a traditional phase detector, two more flip-flops are used for PLL lock detection. More precisely, they implement a socalled `cycle slip' detection.

When the PLL is in lock, Clk1 and Clk2 have identical frequency, but their phase difference can show variations. The PLL will try to maintain a phase difference close to zero, as result of the `ideal integrator' functionality of our low-pass filter. Identical frequency means that between every two edges of Clk1, precisely one edge of Clk2 will occur. After an edge has occurred on both Clk1 and Clk2, both left flip-flops are reset by the nand-gate. Only when two edges occur on Clk1 without an intermediate edge on Clk2, the flip-flop in the cycle slip detector will become set. This can only occur if Clk1 has a higher frequency than Clk2.

An additional RC timing constant in the actual circuit ensures that the flip-flops in the cycle-slip detection remain set for at least about half a second. A single bi-color LED is used for a visual indication on the PLL behavior: