Input Receiver

Interface

Most CD players can be connected to a DAC via SPDIF (Sony Philips Digital Interface). This is an electrical interface using a 75 Ohm coaxial cable. The audio data is transmitted via a DC free encoding algorithm, hence transformer coupling can be used to eliminate LF ground loops.

According to the SPDIF standards an output of a digital source should be transformer coupled (which ensures that the output signal is DC-free). The CS8412 input circuit uses a RS422 receiver, with a Schmitt trigger incorporated to add hysteresis (50mV), which prevents noisy signals from corrupting the phase detector (i.e. prevent jitter). The Crystal input receiver can decode differential as well as single ended inputs. Mainly two manners of connecting are suggested by the data-sheets, transformer coupled or not transformer coupled. The advantages of transformer coupling are RF common mode rejection, high-pass filtering, and isolation from the ground loop, which can have a positive effect on the jitter performance. The transformer should be capable to operate from 1.5 to 7 MHz, which is equal to 25kHz to 55kHz audio signals. With a turns ratio of 2, the voltage at the input receiver chip is doubled, and becomes symmetrical. The main advantage is increased LF noise rejection and increased slope which might reduce jitter at the reception of the input signal.

Input receiver

The physical connection between source and destination is established by an input receiver. Such an input receiver generates two serial audio data streams and the required clock signals. These clocks are generated by an internal PLL that locks on the clock of the transport. If non-audio data is applied (e.g. a CD-ROM is put in the transport) the input receiver mutes the output data. When we started our project, roughly two well-known candidates were publicaly available, the Yamaha YM3623 and the Crystal CS8412. A choice between these two input receiver had to be made.

The first motivation for our choice originates from the jitter performance as specified by the data sheets of these products, which is better for the Crystal (200ps RMS on the master clock). Some people on the net explicitly warn for the very bad performance of the Yamaha in this aspect.

The second motivation is related to the circuitry needed to obtain an operational implementation of an input receiver. The Yamaha input receiver requires an external crystal clock circuit to keep the input receiver in lock when no SPDIF data arrives. It also requires amplification of the 0.5 Volt input signal towards 5 Volt. The Crystal already contains amplication and internal lock circuitry.

The third motiviation is based on some of our listening experiences. WeÕve heard a very good DIY DAC implementation from Morten Simonsen (which in a modified form has been implemented in a Copland CD players) containing a Crystal input receiver, which sounded very convincing, and hence concluded that with the Crystal input receiver DAC implementations can be made. The way the Crystal input receiver should be connected to the remainng digital circuitry of our DAC will be discussed in the next chapter. In this chapter only attention will be paid to those parts involved with the physical connection between source and destination.

Hence, the CS8412 input receiver of Crystal Semiconductors is used. The internal structure of the 8412 is shown below:

See Crystal's web site for more details.

Implementation considerations

The consumer audio output mode M3M2M1M0 should be set to 0101, SEL should be high, and CS12 should be either high or low. An additional capacitor and resistor are needed to establish a filter for the PLL which is implemented internally.

W.r.t. implementation, special attention has been paid to:

• Va+. A separate low noise regulator feeds the analogue section of the chip. In an article on the rec.audio.tech internet news group, the following onformation from Crystal was given:
  
  The best way to route the part is to use a single ground plane and drop the AGND pin directly into it. The local bypass for Va+ should be routed directly between Va+ and AGND with the highest freq. caps closest to the pins and the 'lytic farthest away. There should be a separate feed from the +5V reg through a 4.7 ohm resistor (or so) or a separate reg can be used as long as its ground pin is routed directly to the AGND pin. With the RC network on the FLTR pin routed directly between FLTR and AGND there will be essentially no induced noise on the FLTR pin to cause additional jitter. There is no real reason to have a separate analog and digital plane using this power feed topology. The reason this pin is separate is to allow the power and loop comp to be provided without adding any additional digital noise to the circuit. There is no galvanic isolation in the IC so AGND and DGND are the same node just kelvin terminated out of the package for separation of current loops.
  
  Despite this information, we tried out a seperation, and we were quite amazed by the audible impact (more rest, better pin-pointing of sources).
  
  
• Filt. In addition to the traditional RC, we added a small capacitor to ground, to reduce jitter on the internal VCO. The FLTR on the CS8412 input receiver is susceptible to injected noise currents as it is a high impedance node in the circuit. Depending on layout and adjacent noise sources, it might help to add a shunting capacitor directly across the FLTR and AGND pins to redirect noise currents to ground. This has the potential for reducing high frequency jitter which may or may not make a difference in any given DAC. The value has to be large enough to do some good but small enough so that it doesn't cause the loop to become unstable.