This page presents a short summary of some of our design choices in the DAC.
A tiny high-frequency input transformer makes the sp/diff receiver less sensitive for spurious common-mode currents which might run along the digital cable from your CD drive. This method of isolation is adopted from the aes/ebu professional version of the sp/diff interface. The transformer creates a nicely symmetrical and differential input signal to the receiver chip, which helps in minimizing the generation of jitter. .
The Crystal CS-8412 chip is used as sp-diff receiver, since at the time of selection it was well-known for its good clock stability, and requires very few external components for proper operation. We have deviated from its standard external PLL filter to improve the clock stability. Nevertheless, we regard its 11.289MHz output clock as our 'dirty' clock signal. .
The SM5842AP from Nippon Precision Circuits inc is used as digital filter. We use it in a mode with 16-bit input, 8x oversampling, and 20-bit dithered output signals. The most important reason to select this chip was its dual-clock feature: It allows an input bit-clock which is independent from the the main operation and output bit-clock, with a word-level buffer in the clock-domain bridge.
We found an extremely stable clock signal to be very important for good sonic performance of our DAC. This is achieved by generating a 'clean clock' with a high-quality VCXO (Voltage Controlled Crystal Oscillator). The voltage control allows a small adjustment of the clock frequency (+/- 0.01%) to match and follow the clock in the CD transport, which was re-generated by the sp-diff receiver as 'dirty clock'.
The voltage control is realised by a newly designed PLL (Phase Locked Loop) circuit, containing a 3rd-order low-pass filter at 2Hz, to ensure a smooth frequency adjustment (low jitter). The PLL design required a significant number of components, as no standard PLL chips could support our demands for higher-order analog filtering, and low control bandwidth at this clock rate.
As this 'clean clock' will react very slowly upon input clock variations, a buffer is required for temporal input signal data storage. In our design this is provided internally in the digital filter.
To obtain full advantage of the stable clock in terms of a clean timing of the dac chips, al their input signals must obey a clean timing (have low jitter). We found (measured) that the standard output signals of the digital filter which normally control the dac chips, show a terrible amount of jitter even if the clock itself was clean. Therefor a separate 'reclock circuit' is introduced, which re-samples all signals between the digital filter and the dac chips. Take a further look at detailed information.
The digital-analog converter chips, are the (single channel) BurrBrown PCM-63 chips in their best (K-) selection. They provide a 20-bit conversion into a current-mode output.
An analog filter is needed to get rid of the high-frequency components in the output signal, related with the 8x oversampled clock (around 353kHz) and multiples of that. We chose a passive 3rd order RLC filter, applied before any amplification. Due to the current-mode output of the DAC, a low-impedance filter is designed, which creates an output voltage by a small resistive load. The actual filter configuration is an RC-L-RC pi-filter, with a butterworth low-pass characteristic. The 2 resistances of 150 ohm are low enough to avoid significant distortion effects due to dac output voltage limitations.
The final amplifier is needed to bring the small voltage from the analog filter upto a level which is common for cinch outputs. A vacuum-tube amplifier stage is used, providing a voltage gain of about 20x. Initially a Golden Dragon E88CC tube was used, later most devices changed over to a Svetlana 6N1P. Upto now, we found this tube output stage to be more transparant in comparison with several attempts for bipolar transistor, field-effect transistor, or opamp-based amplifiers.
To minimize cross-talk effects between the digital and the analog circuitry, the digital circuitry has its own power supply, including its own mains transformer. A clean power supply is required for low jitter, as gate delays strongly depend upon the supply voltage. Therefor 7 voltage regulator IC's are used, each responsible for a small section of the design. Furthermore a clean circuit operation is obtained by applying a small ferrite bead in series with the supply of each digital IC, a decoupling capacitor next to each IC, and series resistances in all digital signal lines. These measures are to improve the EMC behavior, by decreasing peak current values, and keeping such currents as local as possible. Listening tests were used for confirming good series resistance values.
A separate power supply and transformer is used for the 'analog' power supply pins of the BurrBrown DAC IC's. It provides four separate stabilized outputs: +5 and -5 volts for left and right. The voltage stabilization is done with a discrete transistor circuit, which operates without feedback to obtain good dynamic behaviour.
Finally, a third power supply is used for the vacuum tube output amplifier, operating at a DC voltage of about 250V, consuming about 10mA. This is made through a rectifier tube (type 6X4) and a CLC-RC filtering. Besides the high-voltage winding, this transformer also provides two low voltage outputs for the rectifier tube filament (directly connected) and the amplifier tube filament (after rectification and voltage stabilisation).
During designing the DAC, it became apparant that a good PCB design was crucial, to avoid RF, EMC and jitter effects.
Copyright © 2001, Marc Heijligers and the DAC group - All rights reserved.